1. Field of the Invention
The present invention relates generally to data caches, and in particular to methods and mechanisms for dynamically sizing a system cache located in a memory controller.
2. Description of the Related Art
Modern day mobile electronic devices often include multiple components or agents sharing access to one or more memory devices. These multiple agents may make large numbers of requests to memory, and as the number of these requests increases, the power consumption of the device increases, which limits the battery life of the device. One approach for reducing power consumption is to try to reduce the number of times that off-chip memory is accessed by caching data in or near the processor.
Conventional caches are typically coupled to or nearby a processor and store data that is frequently accessed by the processor to reduce latency. Caches tend to consume large amounts of power, which is a valuable commodity in mobile electronic devices. Therefore, techniques to decrease the power consumption of caches are desired for reducing the overall power consumption of ICs and other electronic devices.